Custom IC / Analog / RF design, Account Technical Executive for HPC accounts
Cadence · San Francisco Bay Area
📍 SAN JOSE💰 $ 248,000 to $ 372,000via workday
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Account Technical Executive (ATX) – Custom IC / Analog / RF (Virtuoso Platform)
At Cadence, we hire and develop leaders and innovators who want to make a meaningful impact on the future of semiconductor design.
Position Overview
As an Account Technical Executive (ATX) focused on Custom IC / Analog / RF design , you will serve as the primary technical leader driving adoption and value realization of the Cadence Virtuoso Platform , including Virtuoso Layout Suite and associated Custom IC design flows.
You will partner closely with strategic sales teams and key customer stakeholders (design leads, CAD teams, and methodology owners) to solve complex custom IC design challenges , with a strong emphasis on layout implementation, analog and mixed-signal productivity, and advanced-node methodologies .
This role also plays a key part in driving next-generation design methodologies by leveraging AI-driven and agent-based workflows , helping customers adopt intelligent automation frameworks that enhance productivity, design quality, and time-to-market.
Key Responsibilities
Lead technical engagement for Custom IC / Analog / RF design flows , with a primary focus on Virtuoso Layout Suite and the broader Virtuoso platform
Partner with customer design and CAD teams to optimize layout productivity, quality, and time-to-market
Drive adoption of advanced capabilities such as: Constraint-driven and automation-assisted layout
Device-level and full-chip layout methodologies
Advanced node layout challenges (FinFET, GAA)
EM and IR-aware layout and parasitic extraction flows
Champion the integration of AI-driven design techniques , including: Agentic AI workflows to automate design exploration, layout optimization, and verification tasks
AI-assisted decision-making for layout trade-offs including PPA, matching, and parasitics
Translate customer pain points into actionable requirements for R&D and product engineering
Provide technical leadership in methodology definition, flow development, and best practices
Influence competitive replacements and expand footprint of Cadence Custom IC solutions
Support executive-level discussions by linking technical value such as PPA, productivity, and risk reduction to business outcomes
Key Qualifications (Custom IC / Virtuoso + AI Focus)
Custom IC and Virtuoso Expertise
Deep hands-on experience with the Cadence Virtuoso Platform , including: Virtuoso Layout Suite (XL, GXL, EXL)
Schematic-driven layout and LVS flows
DRC and physical verification integration
Strong knowledge of custom analog and mixed-signal layout techniques , including: Device matching, symmetry, common centroid, and shielding
Parasitic-aware layout for high-performance analog and RF circuits
Experience with the Spectre simulation environment and layout-to-schematic integration
Familiarity with PCell development , layout automation, and scripting (SKILL preferred)
Agentic AI and Intelligent Design Automation
Strong understanding of AI and machine learning applications in semiconductor design , specifically: Agentic AI frameworks such as multi-agent systems, goal-driven automation, and autonomous optimization
AI-assisted layout generation and design space exploration
Intelligent automation of repetitive design and verification tasks
Experience or demonstrated interest in: Applying AI to EDA workflows, CAD flows, or design methodology optimization
Working with data-driven or reinforcement learning-based optimization approaches
Ability to bridge AI innovation with practical design flows, translating emerging technologies into deployable customer solutions
Design and Methodology Expertise
5–10 or more years of experience in: Custom IC, Analog, or RF design or layout engineering
Mixed-signal design flows at block and full-chip level
Deep understanding of: Analog and RF design flows from schematic to signoff
Physical verification, extraction, and post-layout simulation
Advanced-node layout challenges and reliability considerations
Experience with layout productivity optimization and methodology deployment at scale
Customer Engagement and Leadership
Proven ability to: Engage deeply with CAD teams, design leads, and senior technical leadership
Identify and articulate technical gaps and business impact
Drive alignment between customer roadmap and Cadence product direction
Strong communication skills with the ability to translate between deep technical detail and executive-level value
Position Requirements
BSEE required, MSEE or higher strongly preferred
5–10 or more years of experience in Custom IC, Analog, or RF design or layout
Demonstrated expertise in Virtuoso-based design environments
Exposure to or strong interest in AI-driven design methodologies and agent-based automation frameworks
Strong collaboration and customer-facing experience
Ability to travel approximately 25 percent, primarily within North America
Location
San Jose
The annual salary range for California is $ 248,000 to $ 372,000 . You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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