Emulation Lead, Senior Principal Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across cloud, AI, enterprise, carrier, and automotive markets, Marvell’s technology leadership in high‑speed connectivity, compute, and storage enables next‑generation systems and architectures. At Marvell, you can influence industry‑defining products, work on complex silicon challenges, and contribute to connectivity technologies that power modern data centers and networks. Your Team, Your Impact The Connectivity Business Unit (BU) develops advanced connectivity silicon that enables high‑bandwidth, low‑latency data movement across compute, memory, and network fabrics. The Connectivity BU product portfolio includes Optical DSPs (ODSP), PCIe/CXL Retimers, high‑speed Ethernet PHYs, SerDes‑based connectivity devices, and Active Electrical Cable (AEC) and Active Optical Cable (AOC) enablement silicon used in AI servers, cloud data centers, and networking platforms. The Connectivity Emulation Team plays a critical role in validating complex connectivity SoCs, accelerating software bring‑up, and enabling pre‑silicon and post‑silicon readiness. As part of the Connectivity Emulation Team leadership, you will define and drive the emulation strategy for connectivity products, ensuring high‑quality tape‑out and efficient downstream validation. What You Can Expect What You Can Expect Define and execute emulation strategies and test plans  for complex connectivity silicon, including ODSP , PCIe/CXL retimers , high‑speed Ethernet PHYs , and AEC/AOC enablement devices , using platforms such as Palladium, Veloce, and Zebu . Work with project leadership and cross‑functional teams to define emulation hardware and software requirements , including platform configurations, transactors, speed bridges, protocol adapters, and firmware/software stacks. Collaborate closely with EDA and emulation hardware vendors  to enable new platforms, maintain tool ecosystems, and drive debug and resolution of hardware, software, and model issues. Develop HW/SW enablement flows and tools  to accelerate RTL validation and improve emulation model usability for early firmware, driver, and system software development. Interface with pre‑silicon validation, architecture, design, firmware, and post‑silicon teams  to optimize validation methodologies and improve overall emulation efficiency. Build and maintain automation flows, scripts, and infrastructure  to improve productivity, scalability, and utilization of emulation environments. What We're Looking For What We’re Looking For Minimum Requirements Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science and a related field with 10+ years of relevant experience , or a Master’s/PhD with 5+ years of experience . Strong hands‑on experience with one or more SoC emulation platforms (Palladium, Veloce, Zebu) or FPGA prototyping platforms, including building and maintaining large‑scale emulation models . Proven background in test planning, simulation, and debug  in Verilog/SystemVerilog  environments. Proven experience with SoC development flows , emulation‑based debug, and system‑level validation . Strong scripting and automation skills  using Python, Perl, Tcl, and UNIX shell . Ability to work effectively across global, cross‑functional teams  and communicate clearly with design, validation, firmware, and vendor partners. Good to Have Experience with emulation of networking devices or mixed‑signal designs , including systems containing PHY or Layer‑2/Layer‑3 functionality. Experience with connectivity‑focused silicon , such as: Optical DSPs (ODSP) PCIe/CXL retimers High‑speed Ethernet PHYs AEC/AOC enablement devices Familiarity with firmware or software bring‑up  using emulation platforms. Prior experience enabling or scaling emulation infrastructure  across multiple projects or product lines. Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected] . Interview Integrity  To support fair and authentic hiring practic