Principal Product Engineer - AI Cloud & Data Center; Platform Transformation Lead

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact The Network and Compute Product Engineering organization at Marvell serves as a core technical leadership function during product development and NPI. The team operates across multiple business units and works closely with design engineering, operations, program management, quality, and leadership to guide technologies from early development into production ready silicon. Product Engineering is responsible for ensuring technical rigor, manufacturability, and readiness for customer deployment. The function exists to connect architecture, silicon behavior, manufacturing reality, and business constraints, and to drive teams toward the technical decisions required for successful productization. The organization plays a key role in enabling next-generation compute and AI-driven infrastructure, supporting products deployed at scale across hyperscale data centers and emerging AI workloads. What You Can Expect As a Principal Product Engineer within the Networking and Compute organization, you are recognized as a technical leader and key stakeholder at the intersection of product engineering and next‑generation test strategy. The rapid evolution of AI infrastructure is driving XPU and hyperscale products into unprecedented performance, volume, complexity regimes, and the methodologies used to validate and qualify them must evolve in kind. In this role, you will help lead that evolution, shaping how Marvell approaches test and productization for its most strategically critical product lines. You are not simply assigned products to manage - you own them; and with them, the technical judgment, influence, and leadership to drive meaningful change across the full end‑to‑end lifecycle. In this role, you will... Drive technical leadership from development through production, ensuring decisions support robust, scalable productization Serve as a primary technical stakeholder during NPI, guiding teams through characterization, debug, qualification, and readiness discussions Align and influence cross‑functional engineering teams toward technically sound, full‑closure solutions during complex problem‑solving efforts Establish and defend test tier architecture across wafer sort, ATE, and SLT, making data‑driven tradeoff decisions that balance coverage, escape risk, quality, and cost‑of‑test Lead ATE‑to‑SLT correlation efforts and drive structured escape analysis, translating yield and quality signals across test tiers into actionable product and process improvements Evaluate, champion, and help scale emerging SLT technologies, including high‑throughput, parallelized test platforms to improve test economics and manufacturing scalability Align and influence cross‑functional engineering teams toward technically sound, full‑closure solutions during complex problem‑solving efforts Define, quantify, and defend product quality, reliability, performance, and cost targets based on data and system‑level impact Lead technical risk assessments and tradeoff discussions, driving clarity and direction across engineering, operations, and management Represent Product Engineering in customer interactions and internal leadership forums, clearly articulating status, risk, and recommended paths forward What We're Looking For Expertise in System Level Test platforms and validation work is a must; hands‑on experience with SLT board design, DUT fixturing, and socket qualification is strongly preferred Deep understanding of test tier architecture across wafer sort, ATE, and SLT, with the ability to make principled tradeoff decisions on coverage, escape risk, and cost‑of‑test Demonstrated experience driving ATE‑to‑SLT correlation, yield learning, and escape containment across test tiers in a volume manufacturing environment Familiarity with emerging high‑throughput SLT methodologies — including parallelization strategies, handler and thermal system constraints, and scalable test content development Deep understanding of the end‑to‑end product lifecycle, with the ability to drive technical decisions that enable scalable productization Strong expertise in structured problem solving and Root Cause Analysis across silicon, test, and manufacturing environments Proven ability to translate complex technical data and analytics into clear, executive‑level narratives and recommendations Hands‑on experience using ATE for silicon characterization, analysis, and debug; experience with 93K is strongly preferred Solid foundation in applied statistics for product characterization, yield improvement, and quality analysis Working knowledge of data analytics and visualization tools such as JMP and SiliconDash or equivalent platforms Strong planning and prioritization skills across multiple parallel efforts; interest in process automation and workflow optimization is a plus   Education and Experience Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of relevant industry experience, preferably in semiconductors OR Master’s degree and/or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of relevant industry experience, preferably in semiconductors Expected Base Pay Range (USD) 136,880 - 205,000, $ per annum The successful candidate’s starting base pay will be determined based on job-related ski