Senior Distinguished Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact At Marvell Technology, we are defining the future of data infrastructure. The Network Switch Business Unit (NSBU) is the powerhouse behind the world’s most advanced cloud, AI, 5G, and enterprise networking products. Our solutions are the backbone of hyperscale data centers, generative AI fabrics, and global-scale networks that demand uncompromising performance. As a Senior Distinguished Engineer, you will be one of the most influential technical leaders in the organization—shaping the architecture of next-generation, high-performance switch ASICs that will set the pace for the entire semiconductor industry. Your work will directly impact the scale-up and scale-out architectures powering the next decade of AI, cloud, and connectivity growth. What You Can Expect This is a role for bold innovators who want to push boundaries, create what hasn’t been built before, and influence the technical direction of a multi-billion-dollar product line. This group is responsible for defining the architecture of Marvell’s next-generation switch ASICs. This team owns: • Product architecture definition • Behavioral modeling • Performance modeling & analysis • Architecture validation • Feature & protocol definition • Cross-functional technical leadership You will collaborate directly with ASIC design, SerDes, firmware, validation, systems engineering, and product teams to bring new switch architectures from concept to silicon and production. In this role, you will have unmatched technical visibility and the opportunity to drive architectural decisions at the highest levels. You will: Lead Architectural Vision Serve as the principal architect for advanced networking ASICs focused on performance, scale-out/scale-up capabilities, power efficiency, and silicon leadership . Define long-term architectural roadmaps for Marvell's next-gen switching platforms serving AI clusters, hyperscale cloud, carrier, and enterprise markets. Drive Cross-Functional Systems Thinking Partner closely with hardware, software, packaging, validation, and system engineering teams to deliver coherent, system-level solutions. Represent the architecture function in executive-level technical reviews and customer engagements. Elevate Engineering Excellence Mentor senior and junior engineers, helping develop the next generation of Marvell’s technical leaders. Foster a culture of innovation, rigor, and forward-looking design across the organization. Work Where Innovation Happens Because this role sits at the core of Marvell’s strategic technology engine, it requires full onsite collaboration in Santa Clara—where silicon, system, and architecture teams work side-by-side to accelerate innovation and execution. What We're Looking For Educational Background Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field required. Master’s or Ph.D. strongly preferred.  Experience & Accomplishments 15+ years  of experience in ASIC architecture and design, preferably in networking, switching, or high-performance SoCs. Demonstrated leadership in driving complex ASIC or multi-die products from concept through delivery. Strong track record of innovation at scale—patents, publications, or industry-recognized contributions. Technical Mastery Deep expertise in: System-level architecture for networking ASICs High-performance switching pipelines, memory subsystems, packet processing, traffic management and buffer management Deep knowledge of Layer 2 / Layer 3 forwarding, QoS, congestion management, and networking protocols . Knowledge of Ethernet IO subsystems (IEEE 802.3 MAC/PCS/FEC) and SerDes Expertise with behavioral and performance modeling, architectural validation, and system-level tradeoff analysis. Strong understanding of system software interaction, control-plane integration, and full-stack implications. Leadership & Collaboration Exceptional communication skills with the ability to explain complex architectural concepts clearly and persuasively Comfortable operating in a fast-paced, highly innovative environment. Proven mentoring capabilities with a passion for developing engineering talent. Expected Base Pay Range (USD) 242,350 - 363,000, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected