Senior Staff DFT Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact CAI Req ID:268 What You Can Expect We are looking for a   Senior Staff DFT Engineer   with   hands-on experience   in scan-based DFT implementation, including   Scan Streaming Network (SSN)   and   IJTAG (IEEE 1687) . This role focuses on   end-to-end scan execution , from insertion and verification through DRC closure, coverage improvement, and final DFT signoff. The ideal candidate will own   scan quality, coverage closure, and DFT signoff   for complex SoC designs. ESSENTIAL DUTIES AND RESPONSIBILITIES Lead hands-on   scan DFT implementation , including: Scan insertion and stitching Scan Streaming Network (SSN) implementation IJTAG (IEEE 1687) insertion and connectivity Perform   scan DFT verification , debug, and DFT DRC closure Debug and resolve scan-related   DRCs, connectivity issues, and control signal problems Run, analyze, and debug   SpyGlass DFT/RTL checks , partnering with design teams to resolve violations Generate, simulate, and debug   ATPG scan patterns Analyze ATPG results and drive   scan coverage improvement and closure Develop and validate   DFT-related timing constraints   (scan, shift, capture, and test modes) Create and maintain   TCL scripts   for scan insertion, ATPG setup, and coverage analysis Optimize scan implementations for   pattern efficiency and test quality Support   hierarchical scan integration   at both block and SoC levels Collaborate closely with   RTL and Physical Design teams   to resolve scan-related issues Support   pre-silicon DFT signoff   and   post-silicon pattern bring-up and debug Assist with   ATE pattern conversion   and scan debug activities What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience. 8+ years   of hands-on experience in   DFT scan implementation Strong expertise with   Siemens Tessent , including: Scan insertion and verification ATPG pattern generation and coverage analysis IJTAG (IEEE 1687) and SSN implementation Strong understanding of: Scan Streaming Network (SSN) IEEE 1149.x, IEEE 1500, and IEEE 1687   standards Proven ability to resolve   scan DFT DRCs   and drive   coverage closure Strong   TCL scripting   skills for automation and flow customization Experience developing and validating   scan and test-mode timing constraints Full   DFT lifecycle experience , from RTL/netlist through silicon debug Strong   debugging, ownership, and problem-solving   skills Excellent   verbal and written communication   skills PREFERRED QUALIFICATIONS Experience with   scan compression   and advanced scan architectures Post-silicon experience , including: Pattern bring-up and debug Silicon characterization and yield learning Experience   mentoring junior engineers   or owning   DFT scan signoff Expected Base Pay Range (USD) 134,390 - 201,300, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected] . Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residen