Staff DFT Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. What You Can Expect We are seeking a   Staff DFT Engineer   with   5+ years of hands-on implementation experience   across   MBIST, BISR, Boundary Scan, and IJTAG . This is a highly   execution-driven role   requiring end-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from   RTL/netlist through post-silicon debug . In this role, you will partner closely with   RTL, Physical Design, and ATE teams   to deliver clean DFT signoff and robust test coverage for complex SoC designs. Perform hands-on   DFT implementation , including: MBIST and BISR   insertion and integration Boundary Scan (IEEE 1149.x)   insertion IJTAG (IEEE 1687)   insertion and connectivity Execute   DFT verification, debug, and DFT DRC closure   using   Siemens Tessent Identify, debug, and resolve   DFT rule violations   at both block and top levels Run, analyze, and debug   SpyGlass DFT/RTL checks , working with design teams to close violations Generate, simulate, and debug   MBIST and logic ATPG patterns Analyze test results and drive   test coverage improvement and closure Develop and validate   DFT timing constraints   for scan, BIST, and test modes Create and maintain   TCL scripts   to automate DFT insertion, verification, and analysis flows Support   hierarchical DFT implementation   and resolve integration issues Collaborate with   RTL and Physical Design teams   to address DFT-related design issues Support   pre-silicon DFT signoff   and assist with   post-silicon pattern bring-up and debug Assist with   ATE pattern conversion and debug   as needed What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience. 5+ years   of hands-on   DFT implementation experience Strong proficiency with   Siemens Tessent , including: MBIST / BISR   insertion and verification Boundary Scan (IEEE 1149.x) IJTAG (IEEE 1687) ATPG pattern generation and coverage analysis Proven ability to resolve   DFT DRCs, connectivity issues, and testability problems Strong   TCL scripting   skills for DFT automation and flow execution Experience developing and validating   scan and test-mode timing constraints End-to-end   DFT lifecycle experience , from RTL/netlist through silicon debug Strong   debugging skills , attention to detail, and sense of ownership Excellent   verbal and written communication   skills PREFERRED QUALIFICATIONS Experience driving   MBIST coverage improvement   and   repair efficiency optimization Post-silicon experience , including: Pattern bring-up and debug Tester pattern conversion Silicon characterization Exposure to   mixed-signal or SERDES DFT , such as   IOBIST or loopback testing Expected Base Pay Range (USD) 113,920 - 170,600, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected] . Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, a