Staff Engineer, Digital Verification

Staff Engineer, Digital Verification Company Description Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with its proprietary Ultrasound-on-Chip™ semiconductor technology and software solutions. Butterfly first proved its technology in the point-of-care ultrasound market – commercializing the world’s first single-probe, whole-body portable ultrasound device, which is now on its best-selling, third-generation: Butterfly iQ3™. The Company combines its advanced hardware with cloud software and AI, an enterprise workflow solution (Compass AI™) and other offerings to drive adoption of affordable, accessible ultrasound. Butterfly also enables third-party development of imaging AI apps through Butterfly Garden™, its software development kit and AI partnership initiative.  In addition to its medical imaging products, Butterfly Embedded™ is the Company’s Ultrasound-on-Chip™ licensing and co-development program designed to enable a new wave of ultrasound-enabled technologies across non-competitive healthcare markets and beyond. Through Butterfly Embedded™, partners can build and scale novel ultrasound applications powered by Butterfly’s proprietary semiconductor chip and software platform. Butterfly’s innovations have been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions and Fast Company’s World Changing Ideas, among other achievements. We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let’s build something extraordinary together! Job Description The role of the Staff Digital Verification Engineer offers the opportunity to work at the core of the product development team alongside company leadership and founders, helping ensure the correctness and robustness of the digital systems that differentiate Butterfly Network’s products. This individual will be responsible for architecting, developing, and executing comprehensive verification strategies for complex digital signal processing blocks, high-speed interfaces, and large system-on-chip (SoC) designs used in next-generation ultrasound imaging platforms. As a senior member of the engineering team, you will drive verification methodology, automation, and infrastructure to enable rapid development and high confidence in silicon correctness. Responsibilities As part of our team, your core responsibilities will include: Architect and develop verification environments for large SoC subsystems using Python-based frameworks, primarily Cocotb. Design and implement self-checking testbenches, constrained stimulus, scoreboards, and coverage infrastructure. Develop bit-accurate reference models (Python) to validate DSP and fixed-point behavior. Verify complex digital signal processing blocks, high-speed interfaces, and system-level datapaths. Collaborate closely with RTL designers to define verification plans, drive coverage closure, and ensure design correctness. Develop and maintain automated regression infrastructure and CI pipelines using GitHub-based workflows. Debug functional issues in simulation, emulation, and post-silicon environments. Contribute to improving the verification methodology, productivity tools, and infrastructure used across the team. Work cross-functionally with architecture, RTL design, firmware, and system teams to ensure robust end-to-end functionality. Qualifications BS/MS/PhD in EE/CE (or equivalent practical experience in digital verification). 8+ years (typical Staff level) experience in digital IC / ASIC / SoC verification. Strong experience building and maintaining Python-based verification environments, particularly Cocotb. Deep knowledge of SystemVerilog and digital design concepts sufficient to effectively verify complex RTL. Proven experience verifying large digital IP blocks or SoC subsystems through full verification closure and tapeout cycles. Experience building self-checking testbenches, scoreboards, monitors, and stimulus generators. Experience developing bit-accurate Python models for algorithm verification and golden reference comparison. Strong debugging skills across simulation, waveform analysis, and root-cause analysis of RTL issues. Experience building automated regression frameworks and CI workflows using GitHub or similar tools. Solid understanding of SoC design challenges including CDC/RDC verification, reset architecture, and power-aware verification. Strong cross-functional communication skills working with RTL designers, architecture teams, and firmware engineers. Preferred (but not required): Experience verifying compute-intensive DSP pipelines (e.g., beamforming, filtering, MAC-heavy datapaths). Familiarity with ultrasound or medical imaging signal processing pipelines. Experience verifying high-bandwidth streaming architectures and large on-chip data pipelines. Exposure to advanced node SoCs (28nm or below). Experience integrating and verifying embedded processors or accelerator subsystems. Experience with ECO or system-level validation flows. Values Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in… Patient-Centric Innovators: Our mission is THE mission. Empowered to Impact: Every voice matters. One Team, One Goal: Unity fuels progress. Growth Champions: We embrace challenges. Action-Oriented Achievers: We follow through, every time. Location Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers. This is a hybrid position and will be based out of our office in either the Greater SF Bay Area or  Burlington, MA.  Benefits and Perks Comprehensive health